As data transfer rates to and from memory become progressively faster, it is becoming increasingly hard to synchronize the timing of the associated data transfers. To optimize system performance, it is desirable to be able to periodically calibrate the timing of the clock signals associated with read and write operations. The purpose of calibration is to compensate for timing variations induced by temperature drift or low-frequency voltage drift during system operation. If timing variations are not compensated, it is possible that the data written to or read from the memory would not be substantially error free.
Existing memory interfaces are typically asymmetric with respect to timing adjustments. For example, in an XDR™ dynamic random access memory (DRAM) interface, the write (read) timing is adjusted at the transmitter (receiver) located on the controller side. In order to correctly adjust the phase position at the controller side, the margin of each pin in the memory interface must be measured. This information is only available at the receiver. One way of obtaining this margin information during a write operation is to send the received bits at the DRAM (which were stored in the memory core) back to the controller through additional read information. This means the write timing adjustment cannot be performed during regular data transmission. Hence, the write timing is typically adjusted by periodically interrupting data transfers to perform calibration operations. Consequently, write buffers of sufficient size are used to store the interrupted data. In addition, flow control from the memory controller is used to schedule the calibration time. Both of these requirements increase the hardware complexity of the memory interface.
Another option is to use the “N+1 technique,” in which an additional link (either physical or phantom) is calibrated while the other N links continue to transmit data. However, this technique either increases cost by adding pins and traces for physical links, or reduces the signaling voltage threshold (Vt) margin in the case of phantom links.
Another possible solution is to use clock-and-data-recovery (CDR) circuitry to automatically generate a clock signal at the receiver. This CDR circuitry generates a clock signal with the correct phase and frequency relative to the transitions in the data stream. CDR circuitry can be complex and, hence, it may not be practical to implement such circuitry on each pin of a memory device (where space is at a premium) to facilitate phase alignment during write operations. Note that the process technology for memory devices is highly specialized to create the memory cells. Also, memory devices are normally built on process technologies that do not offer the same level of interconnect metallization as compared to controller devices. Both of these issues make the implementation of complex circuits on memory devices area-inefficient, thereby adding to the cost of memory devices, which are quite cost-sensitive.
Hence, what is needed is a method and an apparatus for efficiently performing timing adjustments for memory operations without adversely impacting the cost of the memory devices used in the system.